1 radiation hardened cmos dual dpst analog switch hs-302rh, HS-302EH intersil?s satellite applications flow? (saf) devices are fully tested and guaranteed to 100krad total dose. these qml class t devices are processed to a standard flow intended to meet the cost and shorter lead-time needs of large volume satellite manufacturers, while maintaining a high level of reliability. the hs-302rh, HS-302EH analog switches are a monolithic device fabricated using radiat ion hardened cmos technology and the intersil dielectric isolation process for latch-up free operation. improved total dose hardness is obtained by layout (thin oxide tabs extending to a channel stop) and processing (hardened gate oxide). these switches offer low-resistance switching performance for analog voltages up to the supply rails. on-resistance is low and stays reasonably constant over the full range of operating voltage and current. on-resistance also stays reasonably constant when exposed to radiation, being typically 30 ? pre-rad and 35 ? post 100krad(si). these devices provide break-before-make switching. specifications specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbers listed below must be used when ordering. detailed electrical specificatio ns for the hs-302rh, HS-302EH are contained in smd# 5962-95812 . functional diagram features ? qml class t, per mil-prf-38535 ? radiation performance -gamma dose ( ) 1 x 10 5 rad(si) ? no latch-up, dielectrically isolated device islands ? pin for pin compatible with intersil hi-302 series analog switches ? analog signal range 15v ? low leakage . . . . . . . . . . . . . . . . . . . . . 100na (max, post rad) ?low r on . . . . . . . . . . . . . . . . . . . . . . . . . . 60 ? (max, post rad) ? low operating power . . . . . . . . . . . . . .100a (max, post rad) pin configurations hs1-302rh, hs1-302eh (14 ld sbdip), cdip2-t14 top view hs9-302rh, hs9-302eh (14 ld flatpack), cdfp3-f14 top view truth table logic all switches 0off 1on n p in d nc gnd v+ v- 1 2 3 4 5 6 7 14 13 12 11 10 9 8 in1 s3 d3 d1 s4 d4 d2 in2 s2 s1 nc gnd in1 s3 d3 d1 s1 v+ v- s4 d4 d2 in2 s2 14 13 12 11 10 9 8 2 3 4 5 6 7 1 july 31, 2013 fn4603.3 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc 2002, 2013. all rights reserved intersil (and design) and satellite applications flow? (saf) are trademarks owned by intersil corporation or one of its subsidi aries. all other trademarks mentioned are the property of their respective owners.
hs-302rh, HS-302EH 2 fn4603.3 july 31, 2013 ordering information ordering smd number (note 2) part number temp. range (c) package (rohs compliant) (note 1) pkg. dwg. # 5962r9581201v9a hs0-302rh-q -55 to +125 die 5962r9581204v9a hs0-302eh-q -55 to +125 die 5962r9581201qcc hs1-302rh-8 -55 to +125 14 ld sbdip d14.3 5962r9581201vcc hs1-302rh-q -55 to +125 14 ld sbdip d14.3 5962r9581204vcc hs1-302eh-q -55 to +125 14 ld sbdip d14.3 5962r9581201qxc hs9-302rh-8 -55 to +125 14 ld flatpack k14.a 5962r9581201vxc hs9-302rh-q -55 to +125 14 ld flatpack k14.a 5962r9581204vxc hs9-302eh-q -55 to +125 14 ld flatpack k14.a hs9-302rh/proto hs9-302rh/proto -55 to +125 14 ld flatpack k14.a hs0-302rh/sample hs0-302rh/sample -55 to +125 die notes: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free soldering operations. 2. specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbe rs listed in the ?ordering information? table on page 2 must be used when ordering..
hs-302rh, HS-302EH 3 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn4603.3 july 31, 2013 for additional products, see www.intersil.com/en/products.html die characteristics die dimensions: (2130m x 1930m x 533m 25.4m) 84 x 76 x 21mils 1mil metallization: type: al thickness: 12.5k ? 2k ? substrate potential: unbiased (di) backside finish: silicon passivation: type: silox (s i o 2 ) thickness: 8k ? 1k ? worst case current density: < 2.0e5 a/cm 2 transistor count: 76 process: metal gate cmos, dielectric isolation metallization mask layout hs-302rh, HS-302EH d3 d1 s1 in1 nc gnd v- d4 d2 s2 in2 s3 v+ s4
hs-302rh, HS-302EH 4 fn4603.3 july 31, 2013 ceramic dual-in-line metal seal packages (sbdip) notes: 3. index area: a notch or a pin one id entification mark shall be located adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identific ation shall not be used as a pin one identification mark. 4. the maximum limits of lead di mensions b and c or m shall be mea- sured at the centroid of the fini shed lead surfaces, when solder dip or tin plate lead finish is applied. 5. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish thickness. 6. corner leads (1, n, n/2, and n/2+1) may be configured with a par- tial lead paddle. for this configur ation dimension b3 replaces di- mension b2. 7. dimension q shall be measured from the seating plane to the base plane. 8. measure dimension s1 at all four corners. 9. measure dimension s2 from the top of the ceramic body to the near- est metallization or lead. 10. n is the maximum number of terminal positions. 11. braze fillets shall be concave. 12. dimensioning and tolerancing per ansi y14.5m - 1982. 13. controlling dimension: inch. bbb c a - b s c q l a seating base d plane plane s s -d- -a- -c- e a -b- aaa ca - b m d s s ccc ca - b m d s s d e s1 b2 b a e m c1 b1 (c) (b) section a-a base lead finish metal e a/2 s2 m a d14.3 mil-std-1835 cdip2-t14 (d-1, configuration c) 14 lead ceramic dual-in-line metal seal package symbol inches millimeters notes min max min max a - 0.200 - 5.08 - b 0.014 0.026 0.36 0.66 2 b1 0.014 0.023 0.36 0.58 3 b2 0.045 0.065 1.14 1.65 - b3 0.023 0.045 0.58 1.14 4 c 0.008 0.018 0.20 0.46 2 c1 0.008 0.015 0.20 0.38 3 d - 0.785 - 19.94 - e 0.220 0.310 5.59 7.87 - e 0.100 bsc 2.54 bsc - ea 0.300 bsc 7.62 bsc - ea/2 0.150 bsc 3.81 bsc - l 0.125 0.200 3.18 5.08 - q 0.015 0.060 0.38 1.52 5 s1 0.005 - 0.13 - 6 s2 0.005 - 0.13 - 7 90 o 105 o 90 o 105 o - aaa - 0.015 - 0.38 - bbb - 0.030 - 0.76 - ccc - 0.010 - 0.25 - m - 0.0015 - 0.038 2 n14 148 rev. 0 4/94
hs-302rh, HS-302EH 5 fn4603.3 july 31, 2013 ceramic metal seal fl atpack packages (flatpack) notes: 1. index area: a notch or a pin one id entification mark shall be located adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identific ation shall not be used as a pin one identification mark. alternately, a tab (dimension k) may be used to identify pin one. 2. if a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. this dimension allows for off-c enter lid, meniscus, and glass over- run. 4. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish th ickness. the maximum limits of lead dimensions b and c or m s hall be measured at the centroid of the finished lead surfaces, when sol der dip or tin plate lead finish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric materi- als shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the me- niscus) of the lead from the bo dy. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. -d- -c- 0.004 h a - b m d s s -a- -b- 0.036 h a - b m d s s e e a q l d a e1 seating and l e2 e3 e3 base plane -h- b c s1 m c1 b1 (c) (b) section a-a base lead finish metal pin no. 1 id area a m k14.a mil-std-1835 cdfp3-f14 (f-2a, configuration b) 14 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - d - 0.390 - 9.91 3 e 0.235 0.260 5.97 6.60 - e1 -0.290-7.11 3 e2 0.125 - 3.18 - - e3 0.030 - 0.76 - 7 e 0.050 bsc 1.27 bsc - k 0.008 0.015 0.20 0.38 2 l 0.270 0.370 6.86 9.40 - q 0.026 0.045 0.66 1.14 8 s1 0.005 - 0.13 - 6 m - 0.0015 - 0.04 - n14 14- rev. 0 5/18/94
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